This invention pertains to a method and an apparatus for removing soldered electronic components from a substrate. More particularly, it relates to non-destructive, low stress removal of chips temporarily soldered to a substrate during Known-Good-Die (KGD) testing and processing of flip chip devices.
As the state of the art advances, devices formed on semiconductor chips become smaller in dimensions and the devices become more densely crowded on the chip. As a result there is an increasingly important need to pretest devices as a quality control measure involving identification and elimination of defective chips before use thereof. To facilitate pretesting, a technology has developed which is commonly referred to as the KGD (Known Good Die) practice in which a chip is bonded to a temporary substrate in a temporary chip attachment (TCA) process wherein, during a testing interval, the chip is mounted temporarily to a chip carrier substrate which has electrical contacts which match contacts on the chip. During the testing interval, the chip is electrically tested through the substrate. After completion of testing, the chip is removed from the substrate for future use. During the testing interval, a burn-in process is used in which the chip to be tested is bonded temporarily to the substrate. It is desirable for the bonds between the substrate and the chip to be mechanically weak, but strong enough to hold the semiconductor chip in place and to maintain good electrical connections during testing. The chip is normally positioned on the substrate so that the electrical contacts, e.g. C4 solder balls (hereinafter referred to as C4's) on the chip are aligned with the corresponding contacts on the substrate so that the C4's make electrical connections between the chip and the substrate.
In one process for the testing of KGD flip chip devices, silicon chips are temporarily attached by solder balls (typically a SnPb alloy, such as 3% tin (Sn) and 97% lead (Pb), referred to as 3/97 solder) to a composite or ceramic substrate (chip carrier) and subjected to electronic component testing and burn-in. Following this testing, the chips are mounted in a first fixture and subjected at ambient temperature to shear forces across the solder balls to remove the chip from the substrate. These forces typically fracture the solder balls, leaving some solder attached to the substrate and the remainder of the solder attached to the chip. Thereafter, the chips are removed from the first fixture, and those, which tested as good, are then mounted in a second fixture for heat processing to liquefy the solder on the chip and reform the solder balls. The resulting chips are then packaged and eventually mounted in an array of chips on another substrate.
A variety of processes and techniques have been devised and described in the art to form a temporary connection between semiconductor chips and substrates, so as to be able to readily separate the chip and the substrate after burn-in tests have been conducted. Several of these are described in U.S. Pat. No. 5,556,024 of Olson et al., commonly assigned for “Apparatus and Method for Removing Known Good Die Using Hot Shear Process” and the teachings thereof are incorporated herein by reference. In the process of the Olson et al. patent, the substrate which is referred to as device carrier and the device are placed in a fixture, heated to the solder liquidus temperature, and the device is then pulled away from the substrate. In one embodiment, after being heated to the solder liquidus temperature, shear forces are applied sufficient to overcome solder surface tension and to separate the die and carrier. Related patents of Olson et al. include U.S. Pat. Nos. 5,707,000; 5,636,781; 5,738,267.
U.S. Pat. No. 6,163,014 to Bergeron et al. for “Apparatus and Method for Non-Destructive, Low Stress Removal of Soldered Electronic Components” describes an apparatus and a method for removing circuit chips from an assembly including one or more circuit chips attached to at least one chip carrier, or substrate. The chips are subjected to static shear with respect to the substrate, and heated to a temperature facilitating shear within a temperature range at which solder connections are solid, such that the chip is sheared off with respect to the substrate at the plane of attachment of the solder to the substrate. In addition, the chips are further heated following disassembly to a temperature at which the solder is liquid to facilitate reforming the solder for subsequent attachment of the chip into an electronic device. In addition the substrate is held within a top plate and the circuit chips are positioned within successive chip cavities within a bottom plate. Each chip cavity includes a load surface separated by a cascade effect pitch with respect to adjacent chip cavities. A cascade effect shear force is sequentially applied to the circuit chips to remove them from the substrate seriatim.
The substrate has reduced pad dimensions, which releases the C4's therefrom, thereby permitting the C4's to remain on the newly tested chips during the removal process so that the chips can be reattached to the final substrate in the product for which they were manufactured. In addition, the removal process is conducted at pre-reflow temperatures, i.e. below reflow temperatures. A linear shearing force is applied to the first substrate carrier by way of a single compression coil spring. This action pushes the substrate forward and forces the chip to press against a shear tab thus pre-loading the C4's on the first chip with a known shear force. The shear force being applied is set to shear the chip when it has been heated to an elevated temperature. Therefore, at room temperature the chip remains connected to the substrate. When the loaded fixture is placed into a furnace and heated to a critical temperature, the C4 joints and the chip are sheared away from the substrate. The heating raises the temperature until it softens the C4 solder balls on all the parts until they allow the shearing force to push the first carrier forward thus shearing the first chip away from the carrier. As this carrier is moved forward by the coil spring, the first substrate makes contact to the second substrate and the remaining coil spring force is applied to the chip on the second carrier. This action continues until all chips on all carriers are sheared seriatim. With the Bergeron et al. process, there is a variation in coil spring force as the coil spring moves the first substrate forward using the Bergeron et al. process, the coil spring force rate changes. Therefore, forces applied to each chip are different. In addition, the first chip in the row is the only chip that receives the maximum shear force at room temperature which results in an inconsistent application of force.
The down side to any of the above processes is yield loss in terms of missing and/or damaged C4's or bottom layer metallurgy (BLM) damage.